Senior RISC-V Digital IP Design Engineer

What is this role about?

Join onsemi’s new and growing RISC-V division and help define and implement configurable and customizable RISC-V CPU IP for real embedded products.

You will participate in the CPU design lifecycle from requirements and architectural exploration through microarchitecture definition, CodAL-based implementation, RTL generation, design reviews, verification support, tape-out, and silicon readiness.

You will work closely with architecture, verification, compiler, firmware, functional safety, security, and SoC integration teams to deliver reusable processor IP with clear performance, power, area, software, and verification trade-offs.

What will be your main responsibilities in the role?

• Define and implement RISC-V CPU microarchitecture in CodAL, a proprietary HDL language used to describe processor microarchitecture and generate RTL.
• Develop configurable processor capabilities, custom instructions, and architecture enhancements tailored to product and workload requirements.
• Translate architecture, product, safety, and security requirements into implementable microarchitecture, design constraints, and reviewable design rationale.
• Design CPU features related to privilege modes, exceptions, interrupts, memory interfaces, debug functionality, processor configurations, and custom instruction interactions.
• Analyze application workloads and identify opportunities to improve performance, efficiency, energy consumption, and software execution.
• Analyze timing, area, power, performance, and code-efficiency metrics to guide implementation and optimization decisions.
• Collaborate with compiler, SDK, and firmware engineers to ensure that hardware features can be used effectively by software.
• Work closely with verification engineers from feature definition through debug, verification closure, and silicon readiness.
• Support requirements traceability and design evidence needed for safety, security, and external assessment activities.
• Help define and evaluate AI-assisted design methods, including their benefits, limitations, quality controls, and safeguards.

Why join us?

• Join a new and growing RISC-V division and help shape its CPU design practices, reusable IP infrastructure, and engineering culture.
• Work on CPU IP that will be implemented in real products and taken through silicon tape-out.
• Develop expertise in RISC-V architecture, configurable CPU IP, custom extensions, functional safety, security, synthesis, DSP, and edge-AI workloads.
• Collaborate with verification teams using proven UVM simulation methodologies and advanced formal verification techniques.
• Help shape responsible AI-assisted design practices where quality, effectiveness, and expert oversight are essential.
• Contribute to CPU technologies for automotive, industrial, security, and edge-AI applications.
• What skills and experience are we looking for?
• Strong experience in CPU, SoC, DSP, accelerator, or complex reusable digital IP design.
• Advanced knowledge of Verilog/SystemVerilog, RTL design, and digital design fundamentals.
• Good understanding of processor microarchitecture concepts such as pipelines, privilege levels, exceptions, interrupts, memory access and debugger capability.
• Experience with microarchitecture definition, implementation trade-offs, design reviews, and design-for-verification practices.
• Ability to translate technical requirements into implementable design features, constraints, and reviewable design evidence.
• Ability to evaluate trade-offs between performance, power, area, timing, software impact, and verification complexity.
• Strong analytical, problem-solving, communication, and cross-team collaboration skills.
• A quality-oriented engineering mindset and willingness to take ownership of assigned design areas.
• RISC-V experience is valuable.
• Experience with security features, functional safety, compiler interaction, AI acceleration, DSP processing, or hardware/software co-design is an advantage.

What are the requirements?

• Strong digital RTL design experience in CPUs, DSPs, accelerators, SoCs or complex reusable IP.
• Advanced Verilog/SystemVerilog and strong microarchitecture fundamentals.
• Ability to reason across performance, power, area, timing, software impact and verification complexity.
• Relevant experience in processor pipelines, interrupts, memory systems, privilege, debug or custom instructions.
• Ability to provide technical guidance and influence architecture discussions across teams.
• RISC-V is valuable; CPU, DSP or accelerator design experience with another architecture is also relevant with motivation to grow into RISC-V.
• Security architecture, functional safety, compiler interaction, AI acceleration or hardware/software co-design experience is beneficial.
• Demonstrated capability to take ownership of complex technical problems and drive solutions from concept through implementation.

• 25 days of vacation + 3 sick days
• Annual bonus and transportation allowance of up to CZK 4,500 per month
• Learning and development opportunities
• For the complete summary of the company benefits please see the link HERE.

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